An innovative low-density parity-check code design with near-Shannon-limit performance and simple implementation

Author

Eroz, Mustafa ; Sun, Feng-Wen ; Lee, Lin-Nan

Author_Institution

Hughes Network Syst., Germantown, MD, USA

Volume

54

Issue

1

fYear

2006

Firstpage

13

Lastpage

17

Abstract

A novel parity-check matrix design for low-density parity-check (LDPC) codes is described. By eliminating the routing problem associated with LDPC codes, the design results in a small implementation area, and the codes have outstanding error-rate performance close to the Shannon limit for a wide range of code rates, from 1/4 to 9/10, and for various modulation schemes such as binary phase-shift keying (PSK), quaternary PSK, 8-PSK, 16-amplitude PSK (APSK), and 32-APSK. As a result, LDPC codes designed with this method have been standardized for next-generation digital video broadcasting.

Keywords

amplitude shift keying; matrix algebra; parity check codes; phase shift keying; telecommunication network routing; 16-amplitude PSK; 32-APSK; 8-PSK; LDPC codes; binary phase-shift keying; code rates; error-rate performance; low-density parity-check code design; near-Shannon-limit performance; next-generation digital video broadcasting; parity-check matrix design; quaternary PSK; routing problem; Concurrent computing; Digital video broadcasting; Engines; Iterative decoding; Modulation coding; Parallel architectures; Parity check codes; Phase shift keying; Sparse matrices; Very large scale integration; Digital video broadcasting (DVB); high-order modulation; iterative decoding; low-density parity-check (LDPC) codes; very-large-scale integration (VLSI) implementation;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/TCOMM.2005.861681

Filename

1576941