An Analog Data Break Interface

This paper describes the interface used for online control of the Princeton-Pennsylvania Accelerator with a PDP-9. The paper is organized into four sections. The first section is concerned with the specifications for the equipment. The requirements are unique because of the cyclic nature of the synchrotron. Section two discusses various I/O techniques and the design compromises they require. The third section deals with the concept of an analog data break interface. The last section is a summary of existing and planned hardware.