A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs

This brief presents a simultaneous bidirectional capacitive coupling transceiver for intertier communication in 3-D integrated circuits. A novel capacitive coupling interconnect structure is proposed. Optimization of the proposed interconnect structure for minimizing parasitic capacitance achieves the voltage swing VSW of 200 mV at the voltage sensing nodes. The data rate of 3 Gb/s/ch is demonstrated in the emulated-3D interconnect. The proposed transceiver consumes 140 μW at 3 Gb/s/ch. The test chip was fabricated in a 65-nm CMOS technology.