A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

Author

Weston, Harry T. ; Banu, Mihai ; Fang, San-Chin ; Diodato, Philip W. ; Stanik, Thomas D. ; Wilford, Paul A. ; Hsu, Frank M.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

27

Issue

7

fYear

1992

fDate

7/1/1992 12:00:00 AM

Firstpage

1041

Lastpage

1049

Abstract

The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data.

Keywords

MOS integrated circuits; VLSI; multiplexing equipment; optical communication equipment; 0.75 micron; 622.08 Mbit/s; SONET applications; VLSI technology; analog interface circuits; fabrication yield; input amplifier; low-speed differential STS-1 data; maser clock input; output driver; phase splitter; standard synchronous optical network; submicrometer NMOS multiplexer-demultiplexer chip set; Clocks; Differential amplifiers; Integrated circuit technology; MOS devices; Optical amplifiers; Optical device fabrication; SONET; Silicon; Standards development; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.142600

Filename

142600