• DocumentCode
    795183
  • Title

    Ciphering hardware for high-speed digital networks: a REDOC III implementation

  • Author

    Noras, J.M.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Bradford Univ., UK
  • Volume
    31
  • Issue
    11
  • fYear
    1995
  • fDate
    5/25/1995 12:00:00 AM
  • Firstpage
    851
  • Lastpage
    852
  • Abstract
    REDOC III, an algorithm for data ciphering with a predicted throughput in hardware of over 1 Gbit/s, is a proposed replacement for DES. A Xilinx 4000 implementation, with simulation results that confirm the potential system performances, is reported
  • Keywords
    cryptography; digital communication; field programmable gate arrays; logic partitioning; 1 Gbit/s; REDOC III implementation; Xilinx 4000 implementation; data ciphering; data security; encryption algorithm; high-speed digital networks; predicted throughput;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950576
  • Filename
    390950
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=795183