Energy-efficient issue queue design

Author

Ponomarev, Dmitry V. ; Kucuk, Gurhan ; Ergin, Oguz ; Ghose, Kanad ; Kogge, Peter M.

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA

Volume

11

Issue

5

fYear

2003

Firstpage

789

Lastpage

800

Abstract

The out-of-order issue queue (IQ), used in modern superscalar processors is a considerable source of energy dissipation. We consider design alternatives that result in significant reductions in the power dissipation of the IQ (by as much as 75%) through the use of comparators that dissipate energy mainly on a tag match, 0-B encoding of operands to imply the presence of bytes with all zeros and, bitline segmentation. Our results are validated by the execution of SPEC 95 benchmarks on a true hardware level, cycle-by-cycle simulator for a superscalar processor and SPICE measurements for actual layouts of the IQ in a 0.18-/spl mu/m CMOS process.

Keywords

CMOS digital integrated circuits; SPICE; comparators (circuits); instruction sets; integrated circuit layout; logic simulation; low-power electronics; multiprocessing systems; 0.18 micron; 0.18-/spl mu/m CMOS process; SPEC 95 benchmarks; SPICE measurements; bitline segmentation; comparators; cycle-by-cycle simulator; design alternatives; energy dissipation; energy-efficient issue queue design; low-power instruction scheduling; low-power superscalar datapath; operand 0-B encoding; out-of-order issue queue; superscalar processors; tag match; true hardware level; Computer science; Encoding; Energy dissipation; Energy efficiency; Hardware; Logic; Out of order; Power dissipation; Registers; SPICE;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2003.814321

Filename

1234398