Packaged 30 Gbit/s data demultiplexing and clock extraction IC fabricated in a AlGaAs/GaAs HBT technology

Author

Runge, K. ; Yu, R.Y. ; Zampardi, P.J. ; Pierson, R.L. ; Wang, K.C. ; Blixt, P. ; Petersen, A.K.

Author_Institution

Rockwell Inst. Sci. Center, Thousand Oaks, CA, USA

Volume

32

Issue

6

fYear

1996

fDate

3/14/1996 12:00:00 AM

Firstpage

588

Lastpage

589

Abstract

The authors have fabricated a research prototype 30 Gbit/s data demultiplexing and clock extraction IC for high speed multigigabit per second optical communication systems. The circuit features a two stage on chip front end limiting amplifier, as well as a master-slave decision circuit, differentiate and rectify circuitry for clock recovery, and a two stage limiting amplifier on the clock input to the decision circuit. The IC was packaged in a hybrid circuit module, and was used in lightwave system experiments that included full PLL timing recovery

Keywords

III-V semiconductors; aluminium compounds; bipolar digital integrated circuits; clocks; decision circuits; demultiplexing equipment; gallium arsenide; heterojunction bipolar transistors; limiters; optical communication equipment; optical phase locked loops; 30 Gbit/s; AlGaAs-GaAs; HBT technology; clock extraction IC; clock recovery; data demultiplexing IC; differentiate circuitry; front end limiting amplifier; full PLL timing recovery; hybrid circuit module; lightwave system experiments; master-slave decision circuit; optical communication systems; rectify circuitry; two stage limiting amplifier;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19960165

Filename

490492