DocumentCode
79611
Title
Corrections to “Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications” [Jan 13 260-267]
Author
Yamada, Tomoaki ; Nakajima, Yoshiki ; Hanajiri, Tatsuro ; Sugano, Tatsuya
Author_Institution
Bio-Nano Electronics Research Centre, Toyo University, Kawagoe, Japan
Volume
60
Issue
12
fYear
2013
fDate
Dec. 2013
Firstpage
4281
Lastpage
4283
Abstract
Due to an oversight in the above paper (ibid., vol. 60, no. 1, pp. 260-267, Jan. 2013), Figs. 4-9 appeared in black and white in print. They should have printed in color, as shown here.
Keywords
Electric potential; Logic gates; MOSFET; Silicon-on-insulator; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2013.2286957
Filename
6654330
Link To Document