A 1.5 GHz highly linear CMOS downconversion mixer

Author

Crols, Jan ; Steyaert, Michel S J

Author_Institution

ESAT-MICAS, Katholieke Univ., Leuven, Heverlee, Belgium

Volume

30

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

736

Lastpage

742

Abstract

A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 μm CMOS process. It takes up 1 mm² of total chip area and its power consumption is 1.3 mW from a single 5 V power supply

Keywords

CMOS analogue integrated circuits; MMIC mixers; UHF frequency convertors; UHF integrated circuits; UHF mixers; operational amplifiers; radio receivers; 1.2 micron; 1.3 mW; 1.5 GHz; 5 V; CMOS mixer topology; downconversion mixer; input bandwidth; linearity; low-frequency opamp; output amplifier; power consumption; third-order intercept point; total chip area; triode region; Bandwidth; CMOS process; Capacitors; Energy consumption; Filters; Linearity; MOSFET circuits; Semiconductor device measurement; Signal processing; Topology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.391112

Filename

391112