• DocumentCode
    796758
  • Title

    High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes

  • Author

    Wang, Zhongfeng ; Ma, Jun

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
  • Volume
    14
  • Issue
    9
  • fYear
    2006
  • Firstpage
    937
  • Lastpage
    950
  • Abstract
    Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. In this paper, we present a hybrid data format-based interpolation architecture that is well suited for high-speed implementation of the soft-decision decoders. It will be shown that this architecture is highly scalable and can be extensively pipelined. It also enables maximum overlap in time for computations at adjacent iterations. It is estimated that the proposed architecture can achieve significantly higher throughput than conventional designs with equivalent or lower hardware complexity
  • Keywords
    Reed-Solomon codes; decoding; interpolation; RS codes; Reed-Solomon codes; high-speed interpolation architecture; hybrid data format-based interpolation architecture; soft-decision decoding; Computer architecture; Digital communication; Hardware; Interpolation; Iterative decoding; Pipeline processing; Polynomials; Reed-Solomon codes; Throughput; Very large scale integration; Parallel architecture; Reed-Solomon (RS) codes; pipeline processing; polynomial interpolation; soft-decision decoding;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2006.884046
  • Filename
    1715327