DocumentCode :
797063
Title :
Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding
Author :
Zhang, Xinmiao
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH
Volume :
14
Issue :
10
fYear :
2006
Firstpage :
1156
Lastpage :
1161
Abstract :
Reed-Solomon (RS) codes are one of the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to hard-decision decoding, soft-decision decoding offers considerably higher error-correcting capability. The Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while maintaining a complexity polynomial with respect to the code word length. In the KV algorithm, the interpolation step dominates the decoding complexity. A reduced complexity interpolation architecture is proposed in this paper by eliminating the polynomial updating corresponding to zero discrepancy coefficients in this step. Using this architecture, an area reduction of 27% can be achieved over prior efforts for the interpolation step of a typical (255, 239) RS code, while the interpolation latency remains the same
Keywords :
Reed-Solomon codes; computational complexity; decoding; error correction codes; interpolation; polynomials; Koetter-Vardy soft-decision decoding algorithm; Reed-Solomon codes; block error-correcting codes; complexity interpolation architecture; hard-decision decoding; polynomials; Artificial satellites; Computer architecture; Computer errors; Decoding; Delay; Error correction codes; Frequency; Interpolation; Polynomials; Very large scale integration; Guruswami–Sudan (GS) algorithm; Koetter–Vardy (KV) algorithm; Reed–Solomon (RS) code; VLSI architecture; interpolation; soft-decision decoding;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2006.884177
Filename :
1715353
Link To Document :
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