A realistic trap distribution model for numerical simulation of amorphous silicon thin-film transistors and phototransistors

Numerical simulation of amorphous silicon phototransistors using the conventional trap distribution model is shown to give drain-to-source currents lower than experimentally reported values by about a factor of ten. Several attempts to optimize the semiconductor parameters to obtain a good agreement between the experimental and simulation data proved unsuccessful. We propose a more realistic model for the trap distribution which consists of both bulk traps and surface traps. Incorporating this model into a two-dimensional device simulator, simulation results in good agreement with experimental data are obtained for both thin-film transistors and phototransistors