A VLSI architecture for the alternative subsampling-based block matching algorithm

A VLSI architecture of the block matching algorithm based on the alternative subsampling method for motion estimation is proposed. The alternative subsampling method reduces the computational complexity by alternatively subsampling the number of pixels within the blocks used to estimate motion vectors, whereas conventional methods limit the number of locations searched. Simulation results show that the performance of this method is very close to full search algorithm. For a subsampling factor of N, this approach can achieve approximately N/2 times of calculation with an additional small overhead associated with the address generator and temporary buffer. In addition, this architecture has about a half of the silicon area compared to Yang´s (1989) architecture