A VLSI architecture for hierarchical motion estimation

Motion estimation is the critical path in compression algorithms, and several dedicated hardware solutions have been proposed for its acceleration. In this paper we present an innovative VLSI architecture for motion estimation that combines a low implementation cost with real-time performance for videoconferencing and DTV standards. To minimize computational load and architecture requirements, we adopt a three-step hierarchical search algorithm, that provides a quality comparable with more expensive full-search techniques. The proposed solution focuses on architectural efficiency by employing a minimum set of functional units (three simple processing units, one minimum unit, and four programmable delay lines), still supporting real-time performance for videoconferencing standards. In addition we show how to combine parallel motion estimation units for backward-forward prediction (MPEG) and for higher throughput standards (DTV)