High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

Author

Cheng, Chao ; Parhi, Keshab K.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN

Volume

53

Issue

10

fYear

2006

Firstpage

1017

Lastpage

1021

Abstract

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost

Keywords

cyclic redundancy check codes; high-speed integrated circuits; integrated circuit design; pipeline processing; cyclic redundancy check; high-speed parallel circuits; iteration bound; linear feedback shift register; look-ahead pipelining; Algorithm design and analysis; Circuits; Clocks; Computer architecture; Costs; Cyclic redundancy check; Hardware; Parallel processing; Pipeline processing; Polynomials; Cyclic redundancy check (CRC); linear feedback shift register (LFSR); pipelining; retiming; unfolding;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.882213

Filename

1715568