A New Operating Scheme by Switching the Polarity of Program/Erase Bias for Partially Oxidized Amorphous-Si-Based Charge-Trap Memory

In this brief, the authors propose a new program/erase (P/E) scheme for NAND-type partially oxidized amorphous-Si (a-Si)-based charge-trap memory in which the P/E voltages are interchanged into negative/positive ones, respectively. In the a-Si memory, the erasing speed was found to be faster than the programming speed, and therefore, the new scheme has been chosen to keep the program speed faster than the erase speed for the NAND operation. The P/E speeds in the new scheme increase at least ten times as those in the conventional P/E scheme. It is also shown that four-level memory states can be achieved via Fowler-Nordheim tunneling by applying programming voltage of -16, -18, and -20 V for each level during only 40 mus together with erasing voltage pulse (+20 V, 1 ms). These results indicate that the new P/E scheme is more effective than the conventional scheme for operating the partially oxidized a-Si-based memories