• DocumentCode
    802242
  • Title

    Opens and Delay Faults in CMOS RAM Address Decoders

  • Author

    Hamdioui, Said ; AL-Ars, Zaid ; Van de Goor, Ad J.

  • Author_Institution
    Fac. of Electr. Eng., Math., & Comput. Sci., Delft Univ. of Technol.
  • Volume
    55
  • Issue
    12
  • fYear
    2006
  • Firstpage
    1630
  • Lastpage
    1639
  • Abstract
    This paper presents a complete electrical analysis of address decoder delay faults "ADFs" caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests
  • Keywords
    CMOS memory circuits; built-in self test; electrical faults; fault diagnosis; logic testing; random-access storage; BIST implementation; CMOS RAM address decoder; address decoder delay fault; electrical analysis; open fault detection; Added delay; Built-in self-test; Circuit faults; Clocks; Decoding; Electrical fault detection; Electronics industry; Read-write memory; Space exploration; System testing; BIST; DFT.; Memory testing; address decoder delay faults; addressing methods; open defects;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2006.203
  • Filename
    1717393
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=802242