Logic Array Design for 250 MHz

This paper describes the design of a logic array in emitter coupled logic (ECL) technology with a complexity of approximately 3000 gates. The circuit is designed for a 250-MHz application and employs ECL 10K and TTL I/O signals on the same chip. Use of an engineering workstation (EWS) for design automation is discussed in great detail. Comparison of simulated data with real data from sample chips shows that good use of an EWS and good software can lead to a correct-by-construction logic array design.