High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging

A novel micro-electromechanical system (MEMS) package has been developed based on modular, reconfigurable components such as substrate, cap, bond region and through-wafer electrical interconnect (TWEI). The paper presents the details of the process for the fabrication of high density, high aspect ratio TWEIs that includes deep dry etching holes through the substrate, depositing an insulation layer and depositing a conductive layer. Two different processes to make the TWEI have been developed: Post-Process where the TWEI is fabricated after the fabrication of MEMS devices and Pre-Process where the TWEI is fabricated before the fabrication of MEMS device. For both processes, the interconnect holes are created by an anisotropic etching process-inductively coupled plasma (ICP) etching. For the post-process, a silicon dioxide layer was deposited in a plasma enhanced chemical vapor deposition (PECVD) chamber to insulate the interconnect holes. For the pre-process, the PECVD process was replaced with a thermal oxide growth step to ensure a more conformal oxide coating. Three different ways to deposit a conductive layer after deposition of an insulation layer have been practiced: sputtering Cu, electroplating Cu and low-pressure chemical vapor deposition (LPCVD) of phosphorus doped polysilicon. The electrical performance of the TWEIs achieved in each way was measured, analyzed and discussed.