• DocumentCode
    803151
  • Title

    Choices of operand truncation in the SRT division algorithm

  • Author

    Burgess, Neil ; Williams, Ted

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
  • Volume
    44
  • Issue
    7
  • fYear
    1995
  • fDate
    7/1/1995 12:00:00 AM
  • Firstpage
    933
  • Lastpage
    938
  • Abstract
    The paper presents an analysis of the number of partial remainder digits and divisor bits that must be examined in the SRT division algorithm. The number of examined digits is found to be the same for both signed digit and 2s complement partial remainder representations, and appears to increase as 3log2r approximately, where r is the radix of the divider. In some cases, it proves advantageous to examine a fractional number of remainder digits by inspecting more positive than negative bits
  • Keywords
    digital arithmetic; mathematics computing; redundant number systems; 2s complement partial remainder representations; Robertson diagrams; SRT division algorithm; computer arithmetic; custom integrated circuit design; divisor bits; fractional number; operand truncation; partial remainder digits; quotient digit selection; radix; remainder digits; signed digit; Algorithm design and analysis; Circuit synthesis; Convergence; Digital arithmetic; Hardware; Iterative algorithms; Notice of Violation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.392852
  • Filename
    392852
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=803151