An 8-b 1.3-MHz successive-approximation A/D converter

Author

Hadidi, Kh ; Tso, Vincent S. ; Temes, Gabor C.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

25

Issue

3

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

880

Lastpage

885

Abstract

A novel successive-approximation analog-to-digital (A/D) converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 0.77 μs. The die area is 3750 mil². This conversion technique can also be utilized in a pipelined A/D converter and enables it to achieve high speed

Keywords

analogue-digital conversion; choppers (circuits); comparators (circuits); 0.77 mus; LSB; MOS amplifiers; chopper-stabilized amplifier; circuit configuration; die area; differential nonlinearity; equal-valued polysilicon resistors; monotonic conversion; offset voltages; pipelined A/D converter; ratioed capacitors; sampling rate; speed; successive-approximation A/D converter; CMOS logic circuits; Circuit faults; Circuit testing; Design automation; Electrical fault detection; Logic devices; Semiconductor device modeling; Solid state circuits; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.102691

Filename

102691