Design and simulation of an efficient adaptive delta modulation embedded coder

An embedded coding version of hybrid companding delta modulation (HCDM) is described that operates from 16 to 48 kb/s in 8 kb/s steps. The embedded HCDM coder employs the explicit noise coding technique to transmit an adaptive PCM (APCM) coded version of the HCDM reconstruction error signal as a supplementary bit stream that may be partly or wholly deleted in transmission. SNR performance with speech input depends critically on the design of the supplemental APCM code and two new coding algorithms are investigated. In algorithm 1, the basic cue for step size adaptation is obtained from the RMS slope energy of the HCDM output whereas in algorithm 2, the HCDM reconstruction error is logarithmically compressed before quantisation and the basic step size is derived from peak input magnitudes. Instantaneous adaptation for both algorithms is achieved by using step size multipliers which are optimised for operation at single fixed bit rates and also for decoding with an unknown number of input bit deletions. Simulation results show that SNR performance is significantly enhanced using either algorithm and a graceful reduction of reconstructed speech quality with progressive bit deletion is achieved over the range from 48 kb/s to 16 kb/s. On the whole, the SNR performance of the embedded HCDM system is superior in comparison with conventional HCDM