Optimum design of IC power/ground nets subject to reliability constraints

The authors formulate and solve the problem of sizing power/ground (p/g) nets in integrated circuits composed of modules, where the nets are routed as trees in the channels between the modules. Constraints are developed to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule requirements. The objective is to minimize the area of the p/g nets subject to these constraints. An optimization technique tailored to this problem is developed. The technique solves the problem more efficiently than the steepest descent method and Newton´s method. Several case studies are presented