• DocumentCode
    805637
  • Title

    Ultrathin gate oxide CMOS on (111) surface-oriented Si substrate

  • Author

    Momose, Hisayo Sasaki ; Ohguro, Tatsuya ; Nakamura, Shin-ichi ; Toyoshima, Yoshiaki ; Ishiuchi, Hidemi ; Iwai, Hiroshi

  • Author_Institution
    Toshiba Corp., Yokohama, Japan
  • Volume
    49
  • Issue
    9
  • fYear
    2002
  • fDate
    9/1/2002 12:00:00 AM
  • Firstpage
    1597
  • Lastpage
    1605
  • Abstract
    The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a (111) surface-oriented Si substrate were investigated and compared with those on a (100) substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the (111) substrate is smaller than that on the (100) substrate and that of p-MOSFETs on (111) is larger than that on (100) until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for (100) and (111) substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the (111) substrate is slightly better than that on the (100) substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4° from (100) axis were investigated. It was found that there are few differences in the mobility between (100) and (100) 4° off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal (100) substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs
  • Keywords
    CMOS integrated circuits; MOSFET; carrier mobility; dielectric thin films; hot carriers; integrated circuit reliability; leakage currents; semiconductor device breakdown; semiconductor device reliability; semiconductor-insulator boundaries; silicon; substrates; tunnelling; (100) Si substrate; (111) surface-oriented Si substrate; 2 nm; CMOS transistors; CMOSFETs; Si; Si-SiO2; TDDB; direct tunneling gate-oxide regime; electrical properties; field mobility; gate leakage current; hot carrier injection; n-MOSFETs; p-MOSFET; reliability; time-dependent dielectric breakdown; ultrathin gate oxide CMOS; CMOS technology; Dielectric breakdown; Dielectric substrates; Hot carrier injection; Leakage current; Logic; Low voltage; MOSFET circuits; Microprocessors; Substrate hot electron injection;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2002.802624
  • Filename
    1027842