Title :
On the nonenumerative path delay fault simulation problem
Author :
Kagaris, Dimitri ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fDate :
9/1/2002 12:00:00 AM
Abstract :
The problem of determining the exact number of path delay faults that a given test set detects in a combinational circuit is shown to be intractable. This result further strengthens the importance of several recently proposed pessimistic heuristics as well as exact exponential algorithms for this nonenumerative problem. A polynomial time pessimistic algorithm which returns higher coverage than algorithms with the same order of complexity and at the same time compacts the test set is also presented
Keywords :
automatic test pattern generation; combinational circuits; computational complexity; delays; fault simulation; logic simulation; NP-hardness; automatic test pattern generation; combinational circuit; exact exponential algorithms; fault simulation; nonenumerative problem; path delay faults; pessimistic heuristics; polynomial time pessimistic algorithm; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Fault detection; Physics computing; Polynomials; Robustness;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2002.801108