Title :
Optimised multiply/accumulate architecture for very high throughput rate digital filters
Author :
McGovern, B.P. ; Woods, R.F. ; McAllister, C.
Author_Institution :
Dept. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
fDate :
7/6/1995 12:00:00 AM
Abstract :
A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits
Keywords :
IIR filters; digital filters; pipeline arithmetic; digital filters; high performance IIR filters; latches; multiply/accumulate architecture; optimised architecture; pipelined multiply-accumulate processor; very high throughput rate;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950823
