A two-chip 1.5-GBd serial link interface

Author

Walker, Richard C. ; Stout, Cheryl L. ; Wu, Jieh-Tsorng ; Lai, Benny ; Yen, Chu-Sun ; Hornak, Tom ; Petruno, Patrick T.

Author_Institution

Hewlett Packard Co., Palo Alto, CA, USA

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1805

Lastpage

1811

Abstract

A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new `conditional-invert master transition´ code and phase-locked loop that provide adjustment-free clock recovery and frame synchronization are described and analyzed. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the serial-HIPPI implementor´s group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers

Keywords

bipolar integrated circuits; emitter-coupled logic; finite state machines; inter-computer links; network interfaces; phase-locked loops; protocols; synchronisation; variable-frequency oscillators; 700 to 1500 MHz; 800 Mbit/s; ANSI standard; HIPPI data; IEEE standard; SCI-FI; adjustment-free clock recovery; bipolar receiver; bipolar transmitter; conditional invert master transition code; cooperating computer interconnection; frame synchronization; handshake protocol; line code; on-chip VCO; parallel data transfer; phase-locked loop; serial link interface; two chip pair; ANSI standards; Clocks; Code standards; Packaging; Phase locked loops; Protocols; Silicon; Synchronization; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173109

Filename

173109