DocumentCode
808023
Title
An experimental 5-Gb/s 16×16 Si-bipolar crosspoint switch
Author
Shin, Hyun J. ; Immediato, Michael J.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume
27
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1812
Lastpage
1818
Abstract
An experimental 16×16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8-μm, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm×3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W
Keywords
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; multiplexing equipment; switching circuits; 0.8 micron; 1 ns; 4.6 W; 420 ps; 5 Gbit/s; RMS jitter; asynchronous crosspoint switch; data path delay; data rate; multiplexer-type architecture; nonblocking crosspoint switch; power dissipation; self-aligned Si-bipolar ECL technology; setup time; three-device crosspoint cell; Bandwidth; Computer architecture; Computer interfaces; Crosstalk; Delay effects; Jitter; Packaging; Switches; Switching circuits; Throughput;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.173110
Filename
173110
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