A high-speed digital neural network chip with low-power chain-reaction architecture

Author

Uchimura, Kuniharu ; Saito, Osamu ; Amemiya, Yoshihito

Author_Institution

NTT LSI Lab., Kanagawa, Japan

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1862

Lastpage

1867

Abstract

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3-mm×14.1-mm die using 0.8-μm CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems

Keywords

CMOS integrated circuits; digital integrated circuits; neural chips; 0.8 micron; 104 ns; 54 mW; CMOS technology; digital synapse units; forward propagation time; high-speed digital neural network chip; large-scale neural network chips; low-power chain-reaction architecture; neurons; polyhedric discrimination neuron; power dissipation; synapse weights; Associate members; CMOS technology; Large scale integration; Large-scale systems; Neural networks; Neurons; Power dissipation; Power system modeling; Semiconductor device modeling; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173116

Filename

173116