DocumentCode
808105
Title
Neuro chips with on-chip back-propagation and/or Hebbian learning
Author
Shima, Takeshi ; Kimura, Tomohisa ; Kamatani, Yukio ; Itakura, Tetsuro ; Fujita, Yasuhiko ; Iida, Tetsuya
Author_Institution
Toshiba Res. & Dev. Center, Kawasaki, Japan
Volume
27
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1868
Lastpage
1876
Abstract
A layered neural net realized with two chips is described. One chip implements 24×24 synapses, a local weight control mechanism, and quantized ±1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given
Keywords
Hebbian learning; VLSI; analogue processing circuits; backpropagation; neural chips; VLSI; analogue chip; drive capability; layered neural net; local weight control mechanism; momentum update; neuro chip; on-chip back-propagation; synapses; weight update; Algorithm design and analysis; Analog circuits; Hebbian theory; Learning systems; Limiting; Neural networks; Neurons; Signal processing algorithms; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.173117
Filename
173117
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