A novel CMOS digital clock and data decoder

Author

Bazes, Mel ; Ashuri, Roni

Author_Institution

Intel Israel Ltd., Haifa, Israel

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1934

Lastpage

1940

Abstract

A novel CMOS digital clock and data decoder (DCDD) is described. The DCDD has been implemented in a commercial Ethernet serial interface (ESI) integrated circuit for the CSMA/CD standard. As a digital implementation, the DCDD is as manufacturable as conventional CMOS digital circuits, unlike decoders based on analog phase-locked loops, which are sensitive to CMOS processing parameters and are, hence, difficult to manufacture. A 32-tap synchronous delay line (SDL) provides the timing reference for the DCDD with a resolution equivalent to that provided by a 320-MHz clock. This phase information is used to digitally recover, using waveform synthesis performed at a 320-MHz rate, the clock and data information from the input data. The DCDD meets the jitter-tolerance requirements of the CSMA/CD standard with the consistency demanded of a commercial integrated circuit

Keywords

CMOS integrated circuits; clocks; data communication equipment; decoding; digital integrated circuits; 1 micron; 32-tap synchronous delay line; CMOS digital circuits; CSMA/CD standard; DCDD; Ethernet serial interface; data decoder; digital clock; jitter-tolerance requirements; resolution; waveform synthesis; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; Clocks; Decoding; Digital circuits; Ethernet networks; Manufacturing processes; Multiaccess communication; Phase locked loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173124

Filename

173124