A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring

Author

Zhong, Guichang ; Xu, Fan ; Willson, Alan N., Jr.

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

Volume

41

Issue

2

fYear

2006

Firstpage

483

Lastpage

495

Abstract

A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-μm CMOS. It performs 8-point to 4096-point complex FFT/IFFT with power-consumption scalability and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.

Keywords

CMOS integrated circuits; fast Fourier transforms; integrated circuit design; logic design; microprocessor chips; multiprocessing systems; 0.25 micron; CMOS process; FFT/IFFT integrated circuit; multilevel reconfigurability; multiprocessor ring; power-consumption scalability; power-scalable reconfigurable processor; ring-structured multiprocessor architecture; single-chip reconfigurable processor; Communication standards; Digital signal processing; Digital signal processors; Energy efficiency; Fast Fourier transforms; Flexible printed circuits; OFDM modulation; Pipelines; Power dissipation; Signal processing algorithms; ASIC; cached-FFT; digital signal processor (DSP); fast Fourier transform (FFT); inverse FFT (IFFT); multi-processor; programmable; reconfigurable; scalable;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.862344

Filename

1583812