Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors

The use of gated resistors as an innovative technique for hardening scaled static RAM (SRAM) designs is examined. Gated resistors are actively clocked polysilicon resistors that are used to provide single-event upset (SEU) hardness. they are placed in the cross-coupled segments of SRAM cells, similar to designs using passive polysilicon resistors. The high-resistance OFF-state of the gated resistors protects the stored cell data from SEUs. However, during write-cell cycles, the gated resistors are clocked into a low-resistance ON-state by a wordline clock signal. The resultant low-resistance current paths reduce the charging time constants of the internal cell nodes, thus preserving the fast write response to the cell. Experimental investigations of gated resistor technology demonstrated the processing capability and device feasibility. The gated resistor process was found to be easy to integrate into a radiation-hardened half-micrometer CMOS process without introducing any process complexities and without negatively affecting functional yield or degrading total dose hardness