Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor

Author

Passlack, M. ; Abrokwah, J.K. ; Droopad, R. ; Zhiyi Yu ; Overgaard, C. ; Sang In Yi ; Hale, M. ; Sexton, J. ; Kummel, A.C.

Author_Institution

Motorola Inc., Tempe, AZ, USA

Volume

23

Issue

9

fYear

2002

Firstpage

508

Lastpage

510

Abstract

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga₂O₃ gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.

Keywords

III-V semiconductors; MOSFET; gallium arsenide; semiconductor device models; semiconductor technology; semiconductor-insulator boundaries; -0.93 V; 0.6 micron; 51 mS/mm; DC transconductance; Ga/sub 2/O/sub 3/ gate oxide; GaAs; GaAs MOS heterostructure FET; GaAs MOS technology; TiWN-Ga/sub 2/O/sub 3/-GaAs-Al/sub 0.75/Ga/sub 0.25/As-In/sub 0.2/Ga/sub 0.8/As -GaAs; device fabrication; enhancement mode; p-channel devices; process flow; self-aligned GaAs MOS-HFET; semiconductor heterojunctions; semiconductor-insulator interfaces; threshold voltage; undoped AlGaAs spacer layer; undoped InGaAs channel layer; Epitaxial layers; Gallium arsenide; HEMTs; Heterojunctions; Indium; MODFETs; MOS devices; MOSFETs; Semiconductor device modeling; Transconductance;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.802591

Filename

1028982