Title :
A behavioral fault simulator for Ideal
Author :
Khoche, Ajay ; Sherlekar, S.D. ; Venkatesh, G. ; Venkateswaran, R.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
Abstract :
A method of performing fault simulation at the behavioral level by propagating faults through behavioral hardware descriptions is presented. The method is accurate because it uses fault models only at the gate level. Since it does not duplicate computations at the behavioral level for each fault, it is, on the average, faster than existing methods. Examples in the Ideal hardware description language are used to discuss the basis for a fast behavioral fault simulator.<>
Keywords :
circuit analysis computing; fault location; specification languages; Ideal hardware description language; behavioral fault simulator; behavioral hardware descriptions; behavioral level; fault models; gate level; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Design automation; Discrete event simulation; Hardware design languages; Logic circuits; Logic gates; Manufacturing;
Journal_Title :
Design & Test of Computers, IEEE
