DocumentCode :
81001
Title :
Design of BiCMOS SRAMs for high-speed SiGe applications
Author :
Xuelian Liu ; LeRoy, Mitchell ; Clarke, Roger ; Chu, Michael ; Aquino, Hadrian O. ; Raman, S. ; Zia, Azhar ; Kraft, Russell ; McDonald, John
Author_Institution :
Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst., Troy, NY, USA
Volume :
8
Issue :
6
fYear :
2014
fDate :
11 2014
Firstpage :
487
Lastpage :
498
Abstract :
This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 μm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a -3.4 and -1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a fT of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.
Keywords :
BiCMOS digital integrated circuits; CMOS memory circuits; Ge-Si alloys; SRAM chips; amplifiers; analogue-digital conversion; buffer circuits; buffer storage; current-mode circuits; current-mode logic; heterojunction bipolar transistors; integrated circuit design; semiconductor materials; 3D technology; 8XP design; ADC systems; BiCMOS SRAM design; CML decoder; CML logic level; CML word line driver; CML-style circuits; CMOS 6T memory cells; HBT BiCMOS technology; IBM 8HP SiGe technology; SRAM buffer memories; SRAM macro; SiGe; analogue-to-digital converter systems; bias strategy; bipolar circuits; bipolar sense amplifier; contemporary fast silicon-germanium HBT BiCMOS process; current mode logic-style circuits; digitalised data; frequency 210 GHz; frequency 4 GHz; frequency 5 GHz; heterogeneous silicon; heterojunction bipolar transistor; high-clock rate computer systems; high-speed silicon-germanium application; interleaved ADC; large-scale ultrawide-bus SRAM; low-level cache memory; next generation; power 0.73 W; power 2.7 W; size 0.13 mum; speed-power tradeoffs; ultrahigh-speed SRAM; voltage -1.5 V; voltage -3.4 V;
fLanguage :
English
Journal_Title :
Circuits, Devices & Systems, IET
Publisher :
iet
ISSN :
1751-858X
Type :
jour
DOI :
10.1049/iet-cds.2013.0375
Filename :
6978093
Link To Document :
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