Testable design of BiCMOS circuits for stuck-open fault detection using single patterns

Author

Menon, Sankaran M. ; Malaiya, Yashwant K. ; Jayasumana, Anura P. ; Rajsuman, Rochit

Author_Institution

Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA

Volume

30

Issue

8

fYear

1995

fDate

8/1/1995 12:00:00 AM

Firstpage

855

Lastpage

863

Abstract

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults

Keywords

BiCMOS integrated circuits; design for testability; fault diagnosis; fault location; integrated circuit design; integrated circuit testing; BJT devices; BiCMOS circuits; charge sharing; delay faults; design for testability; glitches; internal nodes; multipattern sequences; single patterns; stuck-open fault detection; timing skews; transistors; two-pattern sequences; vector; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Design for testability; Electrical fault detection; Fault detection; Logic; Power dissipation; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.400427

Filename

400427