A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor

A design of a 10-bit 27.8 kS/s 0.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage design. To facilitate ultra-low voltage operation, a bulk-driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to relieve non-linearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal-to-noise distortion ratio and 8.4-bit effective number of bits resulting in a figure-of-merit of 2.67 fJ/conversion-step.