Title :
Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation
Author :
Sun, Shih-Wei ; Tsui, Paul G Y
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
fDate :
8/1/1995 12:00:00 AM
Abstract :
A fundamental limit of CMOS supply-voltage (Vcc) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (VT). Based on the data extracted from a sub 0.5 μm logic technology, the variation of ring-oscillator propagation-delay (Td) significantly increases as Vcc is scaled down towards the MOSFET VT. An empirical power-law relationship was then derived to describe the scattering of circuit speed (ΔTpd ) as a function of MOSFET VT variation (ΔVT ) and (Vcc-VT). Agreement between the model and the experimental data was established for Vcc values from 4.0 to 0.9 V. This fundamental limit of CMOS Vcc, scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable systems and battery-based equipment
Keywords :
CMOS integrated circuits; MOSFET; delays; integrated circuit design; integrated circuit modelling; 0.5 micron; 0.9 to 4 V; CMOS supply voltage scaling; MOSFET threshold voltage variation; circuit speed; empirical power law relationship; model; ring oscillator propagation delay; CMOS logic circuits; CMOS technology; Data mining; Delay; FETs; Inverters; MOSFET circuits; Power MOSFET; Scattering; Semiconductor device modeling; Sun; Virtual manufacturing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
