Title :
Parallel VLSI computing array implementation for signal subspace updating algorithm
Author :
Abdallah, Ali Hussein ; Hu, Yu Hen
Author_Institution :
Teleco Oilfied Services Inc., Meriden, CT, USA
fDate :
5/1/1989 12:00:00 AM
Abstract :
The parallel VLSI computing array implementation is discussed for novel signal subspace iteration algorithm (SSIA) proposed by I. Karasalo (1986). By making use of a sparse structure, a linearly connected VLSI computing structure is developed for the singular valve decomposition operation used in this algorithm. It is first shown that by making use of a sparse structure matrix the computing time of this algorithm for a single processor can be reduced from O(N3) to O(N2), where N is the dimensional of the signal subspace. Then it is shown that the parallel architecture can reduce the overall computing time for single-valued decomposition from O(N2) to O(N)using O(N) processors. This reduces the total computing time of SSIA from max (O(K 2), O(N2K)) with a single processor to O(K) with O(N 2) processors, where K is the dimension of the covariance matrix
Keywords :
VLSI; computerised signal processing; parallel architectures; covariance matrix; iteration algorithm; parallel VLSI computing array; parallel architecture; signal subspace updating algorithm; singular valve decomposition; sparse structure matrix; Concurrent computing; Covariance matrix; Frequency estimation; Matrices; Semiconductor device noise; Semiconductor process modeling; Signal processing; Signal processing algorithms; Singular value decomposition; Very large scale integration;
Journal_Title :
Acoustics, Speech and Signal Processing, IEEE Transactions on