Title :
The impact of process noise on VLSI process improvement
Author_Institution :
Sch. of Int. Relations & Pacific Studies, California Univ., San Diego, La Jolla, CA, USA
fDate :
8/1/1995 12:00:00 AM
Abstract :
Process improvement is critical to commercial success in VLSI fabrication, especially during ramp-up. This paper investigates one of the factors-process noise-that drives the success of process improvement. Split-lot controlled experiments are vulnerable to confounding by experimental noise, caused by process variability. Fabs with low noise levels have a higher potential for learning (and hence improving their production processes) than high noise fabs. Detailed probe yield data from five semiconductor fabs were examined to estimate process noise levels. A bootstrap simulation was used to estimate the error rates of identical controlled experiments conducted in each fab. Absolute noise levels were high for all but the best fabs, leading to lost learning. The magnitude of lost learning is estimated numerically; it ranges from ten percent to above one hundred percent of the theoretically possible learning in an experiment. In some cases, experiments are little better than coin flipping. Standard statistical methods are either expensive or ineffective for dealing with these high noise levels. Some alternative nonstatistical countermeasures are recommended
Keywords :
VLSI; circuit optimisation; digital simulation; integrated circuit manufacture; integrated circuit yield; semiconductor process modelling; VLSI fabrication; VLSI process; bootstrap simulation; nonstatistical countermeasures; probe yield data; process improvement; process noise; production processes; Error analysis; Fabrication; Noise level; Probes; Production; Sampling methods; Semiconductor device noise; Statistical analysis; Very large scale integration; Yield estimation;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on