DocumentCode :
813931
Title :
Addressing useless test data in core-based system-on-a-chip test
Author :
Gonciari, Paul Theo ; Al-Hashimi, Bashir ; Nicolici, Nicola
Author_Institution :
Dept. of Electron. & Comput. Sci., Univ. of Southampton, UK
Volume :
22
Issue :
11
fYear :
2003
Firstpage :
1568
Lastpage :
1580
Abstract :
This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chain designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and leads to the tradeoff between the test bus width and the volume of test data in multiple scan chain-based cores. Ultimately, this tradeoff influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed which, by dividing the wrapper scan chains (WSCs) into two or more partitions, and by exploiting automated test equipment memory management features, reduces the amount of useless test data. Extensive experimental results using ISCAS´89 and ITC´02 benchmark circuits are provided to analyze the implications of the number of WSCs in the partition, and the number of partitions on the proposed methodology.
Keywords :
automatic testing; boundary scan testing; integrated circuit testing; logic testing; production testing; system-on-chip; chains; core-based system-on-a-chip test; multiple scan chain designs; multiple scan chain-based cores; padding bits; test access mechanism; test bus width; test data; test memory requirements; test methodology; test time; useless test data; wrapper scan chains; Algorithm design and analysis; Automatic testing; Circuit testing; Computer science; Costs; Memory management; Partitioning algorithms; System testing; System-on-a-chip; Test equipment;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.818376
Filename :
1240095
Link To Document :
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