DocumentCode
814558
Title
Design of stuck-open fault testable CMOS complex gates
Author
Tsiatouhas, Y. ; Haniotakis, Th ; Halatsis, C. ; Arapoyanni, A.
Author_Institution
Dept. of Inf., Athens Univ., Greece
Volume
32
Issue
4
fYear
1996
fDate
2/15/1996 12:00:00 AM
Firstpage
315
Lastpage
317
Abstract
Tests that detect transistor stuck-open (TSOP) faults independent of timing skews in input changes may not exist for all TSOP faults in CMOS complex gates. A new design method is presented which does not require any extra hardware or test inputs to improve the testability of a CMOS complex gate
Keywords
CMOS logic circuits; design for testability; fault location; logic design; logic gates; logic testing; CMOS complex gates; design; testability; timing skews; transistor stuck-open faults;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960247
Filename
490941
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