A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies

Reliability and yield of CMOS integrated circuits are becoming more and more dependent on interconnect elements (contacts, vias, and metal lines). These are therefore considered to represent one of the main limits to the future scaling down of integration processes. Indeed, the continuous growth of semiconductor technology integration density has led to billions of transistorson a single chip and, hence, the evaluation of process yield asks for failure rate sensitivity in the order of 1 fault per billion. This paper presents a test structure which allows evaluating the contribution of interconnects to reliability and manufacturing yield degradation in high-density CMOS technologies. The test structure is based on a suitable array of contacts and vias, and has been conceived to measure the statistical distribution of interconnect failures. The main advantages of the proposed test structure are: the reduced number of test pads required measuring an extremely high amount of contacts and vias; the high sensitivity, which allows also resistive contacts or vias to be identified; and the possibility to determine the physical location of interconnect faults, thus simplifying the subsequent physical failure analysis. The test structure was integrated in 130 nm CMOS technology. Experimental results demonstrate the effectiveness of the proposed solution.