Multilayer and multiproduct masks: cost reduction methodology

The cost of reticles is growing twice as fast as the overall cost ofnew process development for technologies beyond the 100-nm node , . In order for the integrated circuit design to continuouslybenefit from the shrinkpath in alignment with Moore´s law , the industry should explore cost-effectiveapproaches for the mask data [(intellectual property (IP)] placement alternativeto the standard methodology of one mask for one layer of one product . The implementation of multi-IPplacements, using multilayer or multiproduct (shuttle) masks, is based oncomplex technical and economical analysis to maximize mask return on investment(ROI) over the product lifetime. The key criteria include the ability to matchlayers or products on one plate with respect to the CD control and patterndensity and the expected time or fab volume prior to the conversion to thededicated mask set for successful products. This work analyzes the links betweenthe IP content of the mask, the product market price, and the wafer volume.As an example, by taking into account the cost of the exposure and of themask, one can show that for 100-nm technology, positive ROI would be achievedfor a product or test vehicle with volume depending on the architecture ofthe multilayer mask set. We compare the key challenges of the two basic multi-IPmask approaches, the multilayer and the multiproduct masks, and discuss thebest conditions for their implementation. Directions for future research arealso proposed.