Title :
A probabilistic fault model for `analog´ faults in digital CMOS circuits
Author :
Favalli, Michele ; Olivo, P. ; Riccò, Bruno
Author_Institution :
DEIS, Bologna Univ., Italy
fDate :
11/1/1992 12:00:00 AM
Abstract :
A probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks is presented. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated, and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults obtained by means of a gate-level fault simulator are discussed for a complex FCMOS benchmark
Keywords :
CMOS integrated circuits; circuit analysis computing; digital integrated circuits; fault location; modelling; probability; analog faults; conductance distributions; detection probability; digital CMOS circuits; fault coverages; fault simulation; gate-level fault simulator; probabilistic fault model; CMOS analog integrated circuits; CMOS digital integrated circuits; Circuit faults; Circuit simulation; Fault detection; Power supplies; Random variables; Semiconductor device modeling; Testing; Voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on