A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

Author

Lee, June ; Sung-Soo Lee ; Kwon, Oh-Suk ; Kyeong-Han Lee ; Byeon, Dae-Seok ; Kim, In-Young ; Kyoung-Hwa Lee ; Lim, Young-Ho ; Choi, Byung-Soon ; Jong-Sik Lee ; Shin, Wang-Chul ; Choi, Jeong-Hyuk ; Suh, Kang-Deog

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Gyeonggi, South Korea

Volume

38

Issue

11

fYear

2003

Firstpage

1934

Lastpage

1942

Abstract

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm² die size and a 0.044-μm² effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V_CC in order to avoid program disturbance issues.

Keywords

CMOS memory circuits; NAND circuits; flash memories; integrated circuit layout; memory architecture; photolithography; 1.8 V; 2 Gbit; 90 nm; CMOS NAND flash memory; CMOS STI process technology; KrF photolithography; NAND cell strings; bitline precharge level; block placement; chip architecture; critical layer patterning; die size minimization; effective cell; higher level integration; mass storage applications; on-cell current; one-sided row decoder; program disturbance avoidance; string select line; CMOS process; CMOS technology; Cellular phones; Costs; Decoding; EPROM; Flash memory; Lithography; Personal digital assistants; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.818143

Filename

1240974