A Linearization Technique for a Transconductor Using Vertical Bipolar Junction Transistors in a CMOS Process

In this paper, a linearization technique for a transconductor using vertical NPN (V-NPN) bipolar junction transistors (BJTs) in a deep n-well CMOS process is proposed to achieve high linearity performance without degrading power efficiency and noise performance. The proposed transconductor consists of a V-NPN BJT pseudodifferential transconductor (PDT) and a V-NPN BJT fully differential transconductor (FDT). The linearity of the proposed transconductor is improved by canceling the negative peak value of gm^´´ in the FDT with the positive one in the PDT and by making overall gm^´´ of the proposed transconductor close to zero. To verify the proposed linearization method, an RF amplifier and a first-order Gm-C low-pass filter adopting the proposed transconductor are designed and implemented in a 0.18-μm deep n-well CMOS process. The implemented RF amplifier and Gm-C low-pass filter achieve 5.8- and 8.5-dB improvements over conventional circuits in the output-referred third-order intercept point, respectively.