BiCMOS circuit technology for high-speed DRAMs

Author

Watanabe, Shigeyoshi ; Sakui, Koji ; Fuse, Tsuneaki ; Hara, Takahiko ; Aritome, Seiichi ; Hieda, Katsuhiko

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

28

Issue

1

fYear

1993

fDate

1/1/1993 12:00:00 AM

Firstpage

4

Lastpage

9

Abstract

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed

Keywords

BiCMOS integrated circuits; DRAM chips; integrated circuit technology; 1 kbit; BiCMOS circuit technology; CMOS DRAM access time; CMOS current mirror circuit; CMOS flip-flop; bit-line sense amplifier; clocked CMOS inverter; differential amplifier; high speed dynamic RAM; impedance-converting; megabit DRAMs; BiCMOS integrated circuits; CMOS technology; Circuit testing; Clocks; Differential amplifiers; Flip-flops; Impedance; Inverters; Mirrors; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.179197

Filename

179197