Exploring SOI device structures and interconnect architectures for low-power high-performance circuits

Vertical integration technology offers numerous advantages over conventional structures. Double-gate transistors can be easily fabricated for better device characteristics, and multiple device layers can be vertically stacked for better interconnect performance. In the paper, the authors explore the suitable device structures and interconnect architectures for multidevice-layer three-dimensional (3D) integrated circuits and study how 3D silicon-on-insulator (SOI) circuits can better meet the performance and power dissipation requirements projected by International Technology Roadmap for Semiconductors (ITRS) for future technology generations. Results demonstrate that double-gate SOI circuits can achieve as much as 20% performance gain and 30% power delay product reduction over single-gate SOI. More important, for interconnect-dominated circuits, 3D integration offers significant performance improvement. Compared to 2D integration, most 3D circuits can be clocked at much higher frequencies (double or even triple). 3D circuits, with suitable SOI device structures, can be a viable solution for future low-power high-performance applications